The Next Silicon Innovation Era

Mapping the RISC-V startup ecosystem leading a new movement in computer chip design

Chances are, unless you’re already in the semiconductor industry, you probably haven’t heard of the term “RISC-V” or know what the letters stand for. Chances are, if you’re like me and blindly believe in the power of phonetics, you might not even know how to pronounce RISC-V.

When I first met with Professor Krste Asanovic, the head of RISC-V.org, on Berkeley’s glorious grounds, I kicked off by saying something highly eloquent. Something like, “So, Mr. Scientist. Tell me what you know about this ‘risk vee’ stuff.”

“Uhh, it’s pronounced ‘five.’” Eloquence everywhere.

“What’s that? Five what?”

“Risk five. RISC-V.”

I didn’t talk much thereafter, yet Professor Asanovic was still kind enough to hold my hand and walk me through an ocean of questions.

What I then thought was going to be a straightforward research project into a new microprocessor technology ended up opening a can of worms (and a couple Coursera classes for computer architecture) that convinced me we’re on the edge of a new wave of silicon innovation, and witness to the kind of semiconductor companies we haven’t seen for a while here in Silicon Valley. Since the good old days, when band gaps meant something . Putting the Silicon back in Silicon Valley.

Simply put, RISC-V is an open-source instruction set architecture (specifically, Reduced Instruction Set Computing, hence RISC), defining the “rules” for software programs to communicate with the physical components of microprocessors like memory and logic units. It’s a major threat for incumbent semiconductor companies that work hard to market incremental gains in their proprietary technology while defending it from competitors and innovation through vast IP portfolios.

While an open source instruction set would be a boon for semiconductor designers working on new compute applications like AR, VR, and machine learning, this kind of implementation in the industry requires a galaxy of support and fabrication services, a unified effort across engineering and design capabilities not just to build functional RISC-V processor but to ramp and integrate them into servers and devices.

The RISC-V concept launched out of UC Berkeley way, way back in 2010. Take a look at the ecosystem built around the RISC-V community that has risen from nothing in less than 8 years:

Though many of these companies are startups, you’ll see a few big names on there who are starting to understand RISC-V before a startup beats them, and preparing for an increasing reality of an open-sourced, highly flexible ISA (instruction set architecture). Western Digital, for example, has taken a bold lead in the future of chipsets from diverse manufacturers and applications, all based on the RISC-V instruction set architecture.

The RISC-V Movement

RISC-V in itself isn’t a marketable technology. By design, it’s a platform that allows anyone — researchers, companies big and small — to build chipsets with an unlimited range of applications on top of a standardized, open-source instruction set.

Now, ISA’s are a unique class of engineering challenge — they’re not necessarily difficult to build, but they are very difficult to build right and in a way that’s both scalable and free from errors. After all, these are the things that manage information flow between the make-believe fantasyland of software and the brutally physical hardware realm, telling gajillions of 1’s and 0’s where to go and every second between the two demands careful housecleaning. CPU history is filled with examples of ISA’s experiencing specific, unforeseen failure modes after mass product deployment. And because the instruction set defines how software communicates with the underlying hardware, patches to the ISA in the field aren’t possible (ergo, hardware is hard).

The challenge of building highly functional ISA’s is therefore a valuable capability, bordering on an art form. And the leading artists — Intel for datacenters, ARM for devices, NVIDIA for GPUs, etc. — have become very big companies in large part because of their ability to both build excellent, extremely reliable ISAs and (most importantly) control what anyone does with those ISAs.

Its this second issue — design control — that’s particularly interesting. When someone wants to build a new class of microprocessor or processor unit, they either have to build out their own ISA or layer their new applications on top of an existing ISA.

The value of RISC-V is for innovators to layer new compute applications on top of a highly capable, reliable, and open instruction set.

RISC-V is the result of the unified effort to design an ISA that is universally accessible and available to use for many devices and applications. Now, anyone can use the RISC-V open-source ISA as a base level to design a chip and integrate it into a computer, decentralizing the authority from a few dominant companies and putting it into the hands of entrepreneurs.

In essence, RISC-V has created a new platform for semiconductor innovation. It’s leveled the playing field for building new chipsets with novel applications — new, potentially risky applications that may not have clear market pull yet but that can launch at the “beta” level without investing millions of dollars to accessing ISA IP or design services.

For entrepreneurs, it’s the sticky matter of identifying which market demands are best satisfied with an open source ISA — where they can be competitive to traditional processor companies — and defining the path for innovative new chip designs that will carry our computing capabilities forward.

So, should you care?

If you’re in the semiconductors industry, absolutely. And if you’re an electronic device manufacturer, absolutely. And if you buy smartphones or laptops… it’s ok if you don’t, but you might see some strange new logos popping up.

If it’s successful in its mission, RISC-V will increase the rate of compute innovation by lowering the barriers to entry for high performance, reliable, fundamental compute technology.

Consumers will see faster, better devices with wild and useful applications — in machine learning, virtual reality, blockchain, who knows!

But behind the scenes, they can thank RISC-V.